I. Field of the Invention
The present invention relates to obtaining and maintaining synchronization with an incoming signal prior to and during the transmission of data. More specifically, the present invention relates to recognizing that a pattern within an incoming demodulated electromagnetic signal has repeated itself (or that some mathematical relationship thereof has been received) a specified number of times, indicating that synchronization has been achieved and that transmitted data is forthcoming. The present invention also more specifically relates to maintaining synchronization with the incoming demodulated signal while data, which is imbedded within the signal, is received.
II. Related Art
The ability to transmit and receive information using a wireless electromagnetic carrier (at, e.g., radio or microwave frequencies) has been known for many decades. A somewhat more recent development, though, is the ability to receive and process binary data using digital technology. One common way that this works in a wireless environment is that an electromagnetic "pattern" is transmitted representing a binary piece of data (i.e., a binary 1 or 0). This pattern transmission may utilize amplitude, frequency or phase modulation.
The constituent pieces of the pattern themselves represent binary values. Thus, a pattern representing several binary values are used to represent a single binary value of data. For example, receipt of the pattern "10111011" may represent the receipt of "011 as data, while its inverse, 1101000100" may represent receipt of "1. " Data is conveyed in this way because of noise and interference associated with wireless transmissions. Otherwise, it would be difficult to determine whether the receipt of a single binary value was data or just noise.
Information on the electromagnetic carrier is thus received as a stream of representative binary 1's and 0's. Each binary 1 or 0 is known as a "chip." Thus, the data being transmitted is in the form of a pattern of chips. It is desirable that a pattern representing a binary piece of data comprise a significant number of chips to reduce the chance that unwanted noise in the electromagnetic information is mistaken for transmitted data.
Applications utilizing the transmission of digital information have become very popular in recent years. One such application which has been getting wide-spread attention is wireless local area networks (wireless LAN's). This technology allows computers to exchange information with each other by transmitting this information as described above. The obvious advantage that wireless LAN's have over other LAN's is that wires are not needed to connect the computers together.
Because the airwaves are already very crowded and heavily used by a variety of technologies, it is difficult to assign a usable band of frequencies for use by wireless LAN'S. Consequently, spread-spectrum technology is often utilized. This technology (which was originally developed for military applications) allows an electromagnetic transmission to be spread throughout many different frequencies which are already assigned to such technologies as radio or microwave devices. Since spread spectrum signals have a low-power spectral density, they generate less interference to other devices tuned to the same frequency.
Spread spectrum technology and wireless LAN's are particularly applicable to notebook and other small portable computers, as these computers are typically purchased for mobility. However, because of their smaller size and dependency on batteries for power, it is important to minimize the amount of circuitry used in receiving the different frequencies. In addition, because of the competitive nature of the computer industry, it is also important that costs associated with spread spectrum devices associated with wireless LAN's be kept to a minimum.
As indicated above, noise and interference are a problem whenever information is transmitted by electromagnetic means. Because of this problem, two important issues must be resolved for data to be successfully received. The first is that the received information needs to be initially recognized as valid information as opposed to noise. This recognition of valid information is known as "synchronization." During this initial synchronization the information acts as a header to indicate that data is about to be received. The second issue is that once synchronization has been obtained, it must be maintained while data is transmitted. This typically involves maintaining alignment of the received information with a reference signal.
Of relevance to both these issues are two general methodologies for determining whether synchronization has been obtained as is being maintained. The first is to analyze the incoming information on the modulated electromagnetic carrier for synchronization purposes prior to converting the information into digital form. The second is to first demodulate the information (i.e., remove the information from the electromagnetic carrier), convert it into digital form and then analyze the digitized information. The advantage of the latter methodology is that it produces a more cost-effective and compact design. Unless stated otherwise, this is the methodology assumed in use in the discussions below.
Regarding the first issue of obtaining synchronization, as indicated above the transmitting source typically transmits a synchronizing header comprising some pre-determined pattern. The received transmission is compared with a reference code (also comprising the pre-determined pattern). A match of the received transmission and reference code indicates that the header has been received and that data is about to be transmitted. The longer the pattern, the less likely it will be mistaken for noise or interference.
Although a longer pattern is obviously preferable, the problem is that the number of components (and thus the size of the circuit) required to detect synchronization increases nearly exponentially as the length of the pattern increases. When dealing with size, cost and power consumption constraints as discussed above, use of a long pattern can quickly become uneconomical.
Consequently, what is needed is a scheme to utilize an adequately long pattern to minimize false detection while also keeping the size of the synchronization detecting circuitry to a minimum. In addition, the circuitry needs to work in an environment where the incoming electromagnetic information has been demodulated first.
Once the demodulated information from the electromagnetic carrier (hereafter referred to as the "input signal") has been synchronized, then data is received. As indicated above, maintaining synchronization of the input signal as data is received is the second important issue which must be resolved to successfully receive the data.
Also as indicated above, typical schemes for conveying data transmit patterns where each pattern represents a 1 or a 0. The patterns used to transmit data are usually (but not always) longer than ones used for obtaining synchronization. However, the mere comparison of a pattern used to transmit data with a reference code in the manner described above is insufficient for maintaining synchronization. This is because fine adjustments are typically made to realign the input signal. This requires determining whether the input signal is being transmitted too quickly or too slowly, which is not deducible from just a pattern comparison.
Schemes which utilize patterns of an input signal to maintain synchronization during data transmission consequently use a somewhat different approach from that used to initially obtain synchronization. One such scheme for maintaining data synchronization utilizes what is known as a delay lock loop. Although this scheme is conventionally used prior to demodulation, it is discussed below in conjunction with FIGS. 1A and 1B with regard to a binary post-demodulation environment.
Referring first to FIG. 1A, a diagram of a conventional delay lock loop is shown. In operation, an input register 102 receives an input signal via line 100. The input register 102 is divided into two sections (124 and 126), each of which contains a chip received from the input signal. The chips shown in input register 102 represent the chips that are in the input register 102 during a time period t.sub.c.
It is contemplated, time period t.sub.c is the time between when a single chip is first detected (in a reference code presumed in substantial alignment with the input signal as discussed below) and the time that the next chip is subsequently detected. Thus, as shown in FIG. 1A, in roughly the first half of time period t.sub.c, section 124 contains chip N while in the second half of that time period it contains chip N+1. Similarly, in the first half of time period t.sub.c section 126 contains chip N-1 while in the second half it contains chip N. Thus, section 124 can be said to contain a later-in-time portion of the input signal while section 126 can be said to contain an earlier-in-time portion. In time periods subsequent to t.sub.c, input register 102 would contain chips N+2, N+3, etc.
A reference code is generated by a code generator (not shown) and transmitted via a line 104. This reference code comprises the same pattern of chips used to transmit the input signal. Thus, it is expected that the chips received by the input signal are the same as the chips of the reference code. In this example, chip N is transmitted by the reference code during time t.sub.c.
During the time period t.sub.c, whatever chips are in sections 124 and 126 are multiplied with chip N of the reference code. Specifically, the reference code is multiplied with the chip in section 124 using multiplier 108 and the reference code is also multiplied with the chip in section 126 using multiplier 110. Typically, multi-sampling would occur where several multiplications actually take place during the period t.sub.c. Although 1's and 0's are actually multiplied, it is conceptually easier to envision 0's as -1's. Consequently, since [reference code chip] N.times.(input register chip) N=1, and [reference code chip]N.times.(N+1 or N-1) would have a 50--50 chance of equaling a 1 or a -1, then if the input signal is aligned with the reference code the number of 1's resulting from multipliers 108 and 110 should be about the same over a given period of time.
If, however, the input signal is not aligned (i.e., not synchronized) with the reference code, then during time period t.sub.c, chip N will be located in either section 124 or section 126 of input register 102 for a longer period of time than in the other section. For example, if the input signal is running more slowly (i.e., it is "late") as compared with the reference code, then chip N will be located in section 124 for a longer period of time than in section 126. If multi-sampling is used within time t.sub.c (and also when subsequent time periods are looked at) then multiplier 108 will yield more 1's than multiplier 110 during this time period. Conversely, if the input signal is running more quickly (i.e., it is "early") as compared with the reference code, then multiplier 110 will yield more 1's than multiplier 108.
Another way of looking at this concept is now described with regard to FIG. 1B. Referring to FIG. 1B, the chips within input register 102 are shown aligned with each other and with the reference code during time period t.sub.c. If the input signal is received too quickly with respect to the reference code, the input signal would "shift" to the right. Therefore, chip N of the reference code would be multiplied with chip N via the "early" part of the input signal (in section 126) more frequently than with chip N via the "late" part of the input signal (in section 124). Thus, more 1's would result from multiplier 110 than from multiplier 108. The greater the difference in 1's, the greater the misalignment.
Thus, the values of the multipliers can be used to determine the direction as well as the magnitude of any misalignment between the input signal and the reference code. However, because of the random nature of the products generated by multiplying N.times.-1) and N.times.(N+1) as discussed above, some scheme is also typically used to average or "smooth" out the results of multipliers 108 and 110 so that a more accurate assessment of the alignment situation can be determined. Such a scheme is explained with regard again to FIG. 1A.
Referring back to FIG. 1A, an adder 112 adds the values from multiplier 108 and multiplier 110. It is contemplated that the adder 112 yields a positive sign if the results of multiplier 108 are positive and a negative sign if the results of multiplier 110 are positive. In this way, a signed value is generated corresponding to whether the input signal is running earlier or later than the reference code.
An integrator 114 is then used to actually "smooth out" what would otherwise appear as "noisy" signals. Consequently, the integrator typically obtains its output value by sampling the input signal over many chips. The output of the integrator 114 thus indicates an average of both the direction and magnitude of misalignment of the input signal. This output is then typically used to adjust the rate of the reference code to bring it into alignment with the input signal so that synchronization can be maintained.
A problem arises with conventional delay lock loops in post-demodulation environments, however, when data is embedded in the input signal. This is because the data is embedded by inverting the pattern in which the signal is sent. In other words, a non-inverted pattern might be equivalent to a binary 0 while an inverted pattern might be equivalent to a binary 1. The effect of this is that the data affects the ability of the reference code to match the pattern of the input signal. More specifically, many of the chips in the input signal will no longer be the same as the corresponding chips in the reference code. Because of this, synchronization cannot be maintained due to changes in the pattern due to data.
Another problem with conventional delay lock loops is that the electromagnetic waves transmitting the data may be using phase modulation. The results of this is that the input signal may have been inverted during transmission. If that is the case, then any misalignment readings will also be inverted (i.e., a "late" input signal will be interpreted as an "early" one).
Consequently, what is needed is some scheme to detect the direction of a misalignment of an input signal with regard to a reference code regardless of whether data is embedded in the input signal, and regardless whether the input signal has been inverted due to phase modulation.